In this issue, as promised, we’re going to look at the FDC

# of CPC Chips

    by James Hoskisson

In this issue, as promised, we’re going to look at the FDC. First open up your CPC. There are several articles that show you how to do this. The FDC is the chip that either says 8272, or 765 on. Okay, that’s done.

The Real Article

To start with I should explain exactly what the FDC is, but I’m not going to. Hah! Oh, okay, but just this once…FDC stands for Floppy Disc Controller (it should actually be FDDC (Floppy Disc Drive Controller), but that’s a bit too long to remember easily.) As you may have gathered by now the FDC chip controls the disc drive.

The actual disc drive interface is pretty simple but that is why the FDC has to do so much. The disc drive basically only indicates information as it comes across it. This means that the FDC can’t just request information from the disc drive, it has to tell it exactly what to do. This leads to the FDC having to be a very complex chip.

What Does This Bit Do?

The FDC is connected to the Z80 like all the other chips. It is a general-purpose chip so it doesn’t have any special connections for the Z80 processor, like the Z80 PIO or SIO. There are several facilities available on the chip that Amstrad decided not to implement, probably to cut the cost of producing the CPC, but I’m just going to explain them so that you know what you’re missing. The FDC is capable of DMA (Direct Memory Access) operation. This requires another chip which controls the data interchange. You can see where the corner was cut there.

If this facility was available to the user it would mean that music could be played while disc accesses were taking place, and such like. It would also free up the processor so it would run faster while it was accessing the disc. The FDC is also capable of selecting up to four disc drives, but since Amstrad only connected one of these lines the CPC can only access two disc drives, unless some extra hardware is added. The hardware isn’t complex. The only reason you can’t have up to four disc drives from the expansion port, without a switch, is because the relevant pins aren’t connected to the edge connector.

The FDC can also operate in FM mode, as well as MFM mode, but only the MFM encryption is implemented in the CPC. These are ways of encoding information before it is saved to the disc. The encoding is needed so that the FDC can tell when a 1 bit starts and when it finishes. The encoding gives the FDC a margin of error because it takes up twice as much space on the disc. The FM encoding isn’t really very useful because it is only used with the single density disc drives, which can’t store as much data as the double density drives on the CPC anyway.

Apart from this everything else works. The FDC can only operate in non-DMA mode. If it did try DMA mode it wouldn’t receive any data because it has no way of accessing the RAM chips or co-ordinating the data transfer. This isn’t really a big disadvantage with the Z80 because the command bytes still need to be sent to the FDC to read/write each track, so it isn’t held up too much.

The FDC operates on the basis that once it receives a command from the processor it goes about its work. The FDC actually requires several bytes in succession before it will do anything. This is more of a safeguard than anything else, although information is transmitted in these bytes. If by some freakish coincidence the drive motor is started and a byte is transmitted to the FDC it won’t do anything.

Even if, by some even more freakish coincidence, the data is exactly the right number of bytes that are needed, containing the exact information on what drive the disc is in etc., it would then require the bytes to be sent at exactly the right time. If this has ever happened to you, you can honestly say that you are the unluckiest person in the world, due to the astronomical chances of this happening by accident.

Pin Assignments of the FDC 765

> > > > > > The Workings

As I have already mentioned the FDC requires multiple bytes before it can be cajoled in to doing what you want, but before we do anything, we have to start the disc drive spinning. This is achieved very simply by OUTing an odd byte to port &FA7E. The only bit that matters on this port is bit 0 (the least significant bit), the other bits are ignored. Hence the odd number required to turn the disk motor on. If bit 0 is 1 the drive motor is started, if it is 0 it is stopped, very simple. The drive motor may be simple but that’s the only thing that is with the FDC. After the drive motor has been started we have to allow some time for it to get up to speed. In assembly language this can be achieved as follows:

> > > > > > >     LD B,7
> > > > > > >     .WAIT1
> > > > > > >     LD HL,0
> > > > > > >     .WAIT2
> > > > > > >     DEC HL
> > > > > > >     LD A,H
> > > > > > >     OR L
> > > > > > >     JR NZ,WAIT2
> > > > > > >     DJNZ WAIT1

This allows some time for the drive motor to get up to speed, although the time varies from disc drive to disc drive. This length of time should be enough for all disc drives. If you want to tailor it to your own disc drive try reducing the time.

If you don’t get any errors it should be fine for future use. Finding out if there were any errors is explained later. Now the disc drive is ready and spinning at full speed, we have to send some commands to the FDC. It would be a good idea to explain how the FDC processes bytes that are sent or read from it at this point. The FDC has three different phases: command, execution, and result. The command phase is when you tell the FDC what to do. The execution phase is when the bytes to be saved, or read, from the disc drive are sent or read from the FDC. The final phase, the result phase, is where the FDC gives information on how the operation went. These bytes have to be read before the FDC will execute any more commands.

FDC Commands

I am now going to list all the commands, followed by the bytes needed for the command, split into the bit significance of the bytes, there might also be a description of the bytes, if you're lucky.

The next bit will be the expected result bytes. I am going to skip the execution phase because it's pretty self explanatory, depending on what the command is. I may include some of them though because the command in question may be a bit ambiguous. Well, here goes:

Read Data: This command basically just reads sectors from the track, that the head is over, into memory. The execution phase consists of the data in each sector.

Results; There are seven result bytes after the execution phase. These are the first three status registers followed by the track number, the head number, the sector number, and the sector size, for the first ID block read in.

Read Deleted Data: This command does exactly the same as the last one except it only reads sector that are marked as deleted. The only difference between deleted data sectors and normal sectors is that they have a byte, which indicates that they are deleted. As far as I know these aren't used on the CPC.

> Write Deleted Data

> This command is just like write data, except the sector is marked with a deleted data address mark. These sectors can be read by Read Deleted Data.

> Results; The results are the same as above.

The FDC has two ports for data exchange. The Main Status register can be found at &FB7E and is an input only port. The register holds information about the FDC and is used to synchronise data reading and writing. It is bit significant as follows:

> > > > > >     Bit           Description
> > > > > >     7	Data Flow Flag
> > > > > >     6	Data Direction Flag
> > > > > >     5	Execution Phase Flag
> > > > > >     4	FDC Busy Flag
> > > > > >     3	FDD 3 busy
> > > > > >     2	FDD 2 busy
> > > > > >     1	FDD 1 busy
> > > > > >     0	FDD 0 busy

The explanation of the descriptions is pretty simple. The Data Flow Flag is set if the FDC is ready for transfer, to or from the chip. This can be as in commands, bytes to be written to/read from the disc, or results. Obviously if the flag is reset the opposite applies.

The Data Direction Flag is set if the FDC is sending information to the CPU (the Z80), and is reset if it expects information from the CPU. This bit can be used to detect which phase the FDC is in because each phase involves a change in the data direction, for the most part. The execution phase flag is more helpful here, though.

<<Here we must say good-bye to the FDC chip for this month. James will tell us more about the FDC status registers next month until then Happy computing. -John>>